// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:13 UTC 2022
//////////////////////////////////////////////////////////////////////////////
//
//  pcs_raw_lane_pcs_xface.v
//
//  Interface logic... overrides, loopbacks, etc.
//
//  Naming convention on input signals...
//  - * is the PCS signal
//  - *_r is the register override value
//  - *_i is the signal connected to the PHY core logic
//
//  Original Author: Ameer Youssef
//  Current Owner:   Gaurav Dubey
//
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
//////////////////////////////////////////////////////////////////////////////
//
//    Perforce Information
//    $Author: thim $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/pcs_raw_lane_pcs_xface.v $
//    $DateTime: 2020/05/14 00:41:08 $
//    $Revision: #85 $
//
//////////////////////////////////////////////////////////////////////////////

`include "dwc_e12mp_phy_x4_ns_pcs_raw_macros.v"
`include "dwc_e12mp_phy_x4_ns_cr_macros.v"

`timescale 1ns/10fs
module dwc_e12mp_phy_x4_ns_pcs_raw_lane_pcs_xface (
// -----------------------------------------------
// PCS INTERFACES
// -----------------------------------------------

// Common interface
input  wire                       mplla_init_cal_disable,
input  wire                       mpllb_init_cal_disable,

// Lane interface
input  wire                       lane_tx2rx_ser_lb_en,
input  wire                       lane_rx2tx_par_lb_en,

// Transmit interface
input  wire                       tx_clk,
input  wire                       tx_clk_rdy,
input  wire [19:0]                tx_data,
input  wire                       tx_data_en,
input  wire                       tx_invert,
input  wire                       tx_reset,
input  wire                       tx_req,
input  wire [1:0]                 tx_pstate,
input  wire                       tx_lpd,
input  wire [1:0]                 tx_width,
input  wire [2:0]                 tx_rate,
input  wire                       tx_mpllb_sel,
input  wire                       tx_mpll_en,
input  wire                       tx_master_mplla_state,
input  wire                       tx_master_mpllb_state,
input  wire                       tx_vboost_en,
input  wire [3:0]                 tx_iboost_lvl,
input  wire                       tx_detrx_req,
output wire                       tx_ack,
output wire                       tx_detrx_result,

// Receive interface
input  wire                       rx_reset,
input  wire                       rx_req,
input  wire [1:0]                 rx_rate,
input  wire [1:0]                 rx_width,
input  wire [1:0]                 rx_pstate,
input  wire                       rx_lpd,
input  wire [5:0]                 rx_ref_ld_val,
input  wire [12:0]                rx_vco_ld_val,
input  wire                       rx_cdr_vco_lowfreq,
input  wire                       rx_adapt_afe_en,
input  wire                       rx_adapt_dfe_en,
input  wire [2:0]                 rx_eq_att_lvl,
input  wire [3:0]                 rx_eq_vga1_gain,
input  wire [3:0]                 rx_eq_vga2_gain,
input  wire [2:0]                 rx_eq_ctle_pole,
input  wire [4:0]                 rx_eq_ctle_boost,
input  wire [7:0]                 rx_eq_dfe_tap1,
input  wire                       rx_adapt_req,
input  wire                       rx_adapt_cont,
input  wire                       rx_offcan_cont,
input  wire                       rx_data_en,
input  wire                       rx_cdr_track_en,
input  wire [2:0]                 rx_los_threshold,
output wire                       rx_clk,
output wire                       rx_ack,
output wire                       rx_los,
output wire                       rx_valid,
output wire                       rx_adapt_ack,
output wire [7:0]                 rx_adapt_fom,
output wire [1:0]                 rx_txmain_dir,
output wire [1:0]                 rx_txpre_dir,
output wire [1:0]                 rx_txpost_dir,
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
input  wire [4:0]                 rx_cdr_ppm_max,
`endif

// Scan interface
input  wire                       scan_mode,
input  wire                       scan_shift_cg,
input  wire                       scan_set_rst,

// Lane number
input  wire [3:0]                 cr_chan_addr,

// -----------------------------------------------
// PHY SIDE PCS XFACE
// -----------------------------------------------

// Common interface
output wire                       mplla_init_cal_disable_i,
output wire                       mpllb_init_cal_disable_i,

// Lane interface
output wire                       lane_tx2rx_ser_lb_en_i,
output wire                       lane_rx2tx_par_lb_en_i,

// Transmit interface
output wire                       tx_clk_i,
output wire                       tx_clk_rdy_i,
output wire [19:0]                tx_data_i,
output wire                       tx_data_en_i,
output wire                       tx_invert_i,
output wire                       tx_reset_i,
output wire                       tx_req_i,
output wire [1:0]                 tx_pstate_i,
output wire                       tx_lpd_i,
output wire [1:0]                 tx_width_i,
output wire [2:0]                 tx_rate_i,
output wire                       tx_mpllb_sel_i,
output wire                       tx_mpll_en_i,
output wire                       tx_master_mplla_state_i,
output wire                       tx_master_mpllb_state_i,
output wire                       tx_vboost_en_i,
output wire [3:0]                 tx_iboost_lvl_i,
output wire                       tx_detrx_req_i,
input  wire                       tx_ack_i,
input  wire                       tx_detrx_result_i,

// Receive interface
output wire                       rx_reset_ate,
output wire                       rx_reset_i,
output wire                       rx_req_i,
output wire [1:0]                 rx_rate_i,
output wire [1:0]                 rx_width_i,
output wire [1:0]                 rx_pstate_i,
output wire                       rx_lpd_i,
output wire [5:0]                 rx_ref_ld_val_i,
output wire [12:0]                rx_vco_ld_val_i,
output wire                       rx_cdr_vco_lowfreq_i,
output wire                       rx_adapt_afe_en_i,
output wire                       rx_adapt_dfe_en_i,
output wire [2:0]                 rx_eq_att_lvl_i,
output wire [3:0]                 rx_eq_vga1_gain_i,
output wire [3:0]                 rx_eq_vga2_gain_i,
output wire [2:0]                 rx_eq_ctle_pole_i,
output wire [4:0]                 rx_eq_ctle_boost_i,
output wire [7:0]                 rx_eq_dfe_tap1_i,
output wire                       rx_adapt_req_i,
output wire                       rx_adapt_cont_i,
output wire                       rx_offcan_cont_i,
output wire                       rx_data_en_i,
output wire                       rx_cdr_track_en_i,
output wire [2:0]                 rx_los_threshold_i,
input  wire                       rx_clk_i,
input  wire                       rx_ack_i,
input  wire                       rx_los_i,
input  wire                       rx_valid_i,
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
output wire [4:0]                 rx_cdr_ppm_max_i,
`endif

// Scan interface
output wire                       scan_mode_i,
output wire                       scan_shift_cg_i,
output wire                       scan_set_rst_i,

// Control Register Bus
//
input  wire                       cr_clk,
input  wire                       cr_rst,
input  wire                       cr_wr_en,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_wr_data,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_rd_data,
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
input  wire [24:0]                cr_sel
`else
input  wire [23:0]                cr_sel
`endif
);


wire rx_reset_int;
wire tx_reset_int;

// Mantis 6933 - Add ATE overrides before other overrides
wire tx_reset_ate;

////////////////////
// Registers
////////////////////

// %%CREG TX_OVRD_IN - Override values for incoming TX controls from PCS
//   OFFSET: 0x0
//   ATTR:   RW, CUST
//   FIELDS:
//     [12] OVRD_EN           - Override enable for all input signals below
//          RESET: 0x0
//     [11] MSTR_MPLLB_STATE  - Override value for tx_master_mpllb_state
//          RESET: 0x0
//     [10] MSTR_MPLLA_STATE  - Override value for tx_master_mplla_state
//          RESET: 0x0
//      [9] MPLL_EN           - Override value for tx_mpll_en
//          RESET: 0x0
//      [8] MPLLB_SEL         - Override value for tx_mpllb_sel
//          RESET: 0x0
//    [7:5] RATE              - Override value for tx_rate
//          RESET: 0x2
//    [4:3] WIDTH             - Override value for tx_width
//          RESET: 0x3
//      [2] LPD               - Override value for tx_lpd
//          RESET: 0x0
//    [1:0] PSTATE            - Override value for tx_pstate
//          RESET: 0x3
//
wire        tx_ovrd_in_en;
wire        tx_master_mpllb_state_r;
wire        tx_master_mplla_state_r;
wire        tx_mpll_en_r;
wire        tx_mpllb_sel_r;
wire [2:0]  tx_rate_r;
wire [1:0]  tx_width_r;
wire        tx_lpd_r;
wire [1:0]  tx_pstate_r;
wire        cr_sel_tx_ovrd_in = cr_sel[0];
wire [15:0] cr_tx_ovrd_in_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(13), .RST_VAL(13'b0_0_0_0_0_010_11_0_11), .MSK_VAL(13'd0))
  tx_ovrd_in_reg (
    .cr_val({
             tx_ovrd_in_en,
             tx_master_mpllb_state_r,
             tx_master_mplla_state_r,
             tx_mpll_en_r,
             tx_mpllb_sel_r,
             tx_rate_r,
             tx_width_r,
             tx_lpd_r,
             tx_pstate_r
             }),
    .cr_rd_data(cr_tx_ovrd_in_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_tx_ovrd_in),
    .cr_self_clr (1'b0)
);

// %%CREG TX_OVRD_IN_1 - Override values for incoming TX controls from PCS, register #1
//   OFFSET: 0x1
//   ATTR:   RW, CUST
//   FIELDS:
//     [12] IBOOST_LVL_OVRD_EN   - Override enable for tx_iboost_lvl[3:0]
//          RESET: 0x0
//   [11:8] IBOOST_LVL_OVRD_VAL  - Override value for tx_iboost_lvl[3:0]
//          RESET: 0xF
//      [7] VBOOST_EN_OVRD_EN    - Override enable for tx_vboost_en
//          RESET: 0x0
//      [6] VBOOST_EN_OVRD_VAL   - Override value for tx_vboost_en
//          RESET: 0x0
//      [5] DETRX_REQ_OVRD_EN    - Override enable for tx_detrx_req
//          RESET: 0x0
//      [4] DETRX_REQ_OVRD_VAL   - Override value for tx_detrx_req
//          RESET: 0x0
//      [3] REQ_OVRD_EN          - Override enable for tx_req
//          RESET: 0x0
//      [2] REQ_OVRD_VAL         - Override value for tx_req
//          RESET: 0x1
//      [1] RESET_OVRD_EN        - Override enable for tx_reset
//          RESET: 0x1
//      [0] RESET_OVRD_VAL       - Override value for tx_reset
//          RESET: 0x1
//
wire        tx_iboost_lvl_ovrd_en;
wire [3:0]  tx_iboost_lvl_ovrd_val;
wire        tx_vboost_en_ovrd_en;
wire        tx_vboost_en_ovrd_val;
wire        tx_detrx_req_ovrd_en;
wire        tx_detrx_req_r;
wire        tx_req_ovrd_en;
wire        tx_req_r;
wire        tx_reset_ovrd_en;
wire        tx_reset_r;
wire        cr_sel_tx_ovrd_in_1 = cr_sel[1];
wire [15:0] cr_tx_ovrd_in_1_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(13), .RST_VAL(13'b01111_00_00_01_11), .MSK_VAL(13'd0))
  tx_ovrd_in_1_reg (
    .cr_val({
             tx_iboost_lvl_ovrd_en,
             tx_iboost_lvl_ovrd_val,
             tx_vboost_en_ovrd_en,
             tx_vboost_en_ovrd_val,
             tx_detrx_req_ovrd_en,
             tx_detrx_req_r,
             tx_req_ovrd_en,
             tx_req_r,
             tx_reset_ovrd_en,
             tx_reset_r
             }),
    .cr_rd_data(cr_tx_ovrd_in_1_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_tx_ovrd_in_1),
    .cr_self_clr (1'b0)
);

// Mantis 6810 - 
// In scan mode, tx_reset_i will have scan muxed onto it, and therefore
// cannot be sent to a synchronizer directly.  Instead send an arbitrary
// register on the same clock domain in scan mode to maintain coverage.
dwc_e12mp_phy_x4_ns_gen_mux tx_reset_mux (
  .out (tx_reset_int),
  .sel (scan_mode_i),
  .d0  (tx_reset_ate),
  .d1  (tx_reset_r)
);

// %%CREG TX_PCS_IN - Current values for incoming TX controls from PCS
//   OFFSET: 0x2
//   ATTR: READ, VOL, CUST
//   FIELDS:
//     [14] DETRX_REQ         - Value from PCS for tx_detrx_req
//     [13] MSTR_MPLLA_STATE  - Value from PCS for tx_master_mplla_state
//     [12] MSTR_MPLLB_STATE  - Value from PCS for tx_master_mpllb_state
//     [11] MPLL_EN           - Value from PCS for tx_mpll_en
//     [10] MPLLB_SEL         - Value from PCS for tx_mpllb_sel
//    [9:7] RATE              - Value from PCS for tx_rate
//    [6:5] WIDTH             - Value from PCS for tx_width
//      [4] LPD               - Value from PCS for tx_lpd
//    [3:2] PSTATE            - Value from PCS for tx_pstate
//      [1] REQ               - Value from PCS for tx_req
//      [0] RESET             - Value from PCS for tx_reset
//
wire        cr_sel_tx_pcs_in = cr_sel[2];
wire [15:0] cr_tx_pcs_in_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(15))
  tx_pcs_in_reg (
    .cr_val({
             tx_detrx_req,
             tx_master_mplla_state,
             tx_master_mpllb_state,
             tx_mpll_en,
             tx_mpllb_sel,
             tx_rate,
             tx_width,
             tx_lpd,
             tx_pstate,
             tx_req,
             tx_reset_int
             }),
    .cr_rd_data(cr_tx_pcs_in_rd_data),
    .cr_sel(cr_sel_tx_pcs_in)
);

// %%CREG TX_OVRD_OUT - Override values for outgoing TX controls to PCS
//   OFFSET: 0x3
//   ATTR:   RW, CUST
//   FIELDS:
//      [2] EN_CTL - Enable override values for all control outputs of this register
//          RESET: 0x1
//      [1] DETRX_RESULT  - Override value for tx_detrx_result
//          RESET: 0x0
//      [0] ACK           - Override value for tx_ack
//          RESET: 0x1
//
wire        tx_ovrd_out_en;
wire        tx_detrx_result_r;
wire        tx_ack_r;
wire        cr_sel_tx_ovrd_out = cr_sel[3];
wire [15:0] cr_tx_ovrd_out_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(3), .RST_VAL(3'b101), .MSK_VAL(3'd0))
  tx_ovrd_out_reg (
    .cr_val({
             tx_ovrd_out_en,
             tx_detrx_result_r,
             tx_ack_r
             }),
    .cr_rd_data(cr_tx_ovrd_out_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_tx_ovrd_out),
    .cr_self_clr (1'b0)
);

// %%CREG TX_PCS_OUT - Current values for outgoing TX status controls from Raw PCS
//   OFFSET: 0x4
//   ATTR: READ, VOL, CUST
//   FIELDS:
//      [0] ACK     - Value from Raw PCS for tx_ack
//
wire        cr_sel_tx_pcs_out = cr_sel[4];
wire [15:0] cr_tx_pcs_out_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(1))
  tx_pcs_out_reg (
    .cr_val({
             tx_ack_i
             }),
    .cr_rd_data(cr_tx_pcs_out_rd_data),
    .cr_sel(cr_sel_tx_pcs_out)
);

// %%CREG RX_OVRD_IN - Override values for incoming RX controls from PCS
//   OFFSET: 0x5
//   ATTR:   RW, CUST
//   FIELDS:
//      [9] ADAPT_DFE_EN    - Override value for rx_adapt_dfe_en
//          RESET: 0x0
//      [8] ADAPT_AFE_EN    - Override value for rx_adapt_afe_en
//          RESET: 0x0
//      [7] OVRD_EN         - Enable override values for all fields in this register
//          RESET: 0x1
//      [6] LPD             - Override value for rx_lpd
//          RESET: 0x0
//    [5:4] PSTATE          - Override value for rx_pstate
//          RESET: 0x0
//    [3:2] WIDTH           - Override value for rx_width
//          RESET: 0x3
//    [1:0] RATE            - Override value for rx_rate
//          RESET: 0x0
//
wire        rx_adapt_dfe_en_r;
wire        rx_adapt_afe_en_r;
wire        rx_ovrd_in_en;
wire        rx_lpd_r;
wire [1:0]  rx_pstate_r;
wire [1:0]  rx_width_r;
wire [1:0]  rx_rate_r;
wire        cr_sel_rx_ovrd_in = cr_sel[5];
wire [15:0] cr_rx_ovrd_in_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(10), .RST_VAL(10'b0_0_1_0_00_11_00), .MSK_VAL(10'd0))
  rx_ovrd_in_0_reg (
    .cr_val({
             rx_adapt_dfe_en_r,
             rx_adapt_afe_en_r,
             rx_ovrd_in_en,
             rx_lpd_r,
             rx_pstate_r,
             rx_width_r,
             rx_rate_r
             }),
    .cr_rd_data(cr_rx_ovrd_in_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_rx_ovrd_in),
    .cr_self_clr (1'b0)
);

// %%CREG RX_OVRD_IN_1 - Override values for incoming RX controls from PCS, register #1
//   OFFSET: 0x6
//   ATTR:   RW, CUST
//   FIELDS:
//      [3] REQ_OVRD_EN        - Override enable for rx_req
//          RESET: 0x0
//      [2] REQ_OVRD_VAL       - Override value for rx_req
//          RESET: 0x1
//      [1] RESET_OVRD_EN      - Override enable for rx_reset
//          RESET: 0x1
//      [0] RESET_OVRD_VAL     - Override value for rx_reset
//          RESET: 0x1
//
wire        rx_req_ovrd_en;
wire        rx_req_r;
wire        rx_reset_ovrd_en;
wire        rx_reset_r;
wire        cr_sel_rx_ovrd_in_1 = cr_sel[6];
wire [15:0] cr_rx_ovrd_in_1_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(4), .RST_VAL(4'b01_11), .MSK_VAL(4'd0))
  rx_ovrd_in_1_reg (
    .cr_val({
             rx_req_ovrd_en,
             rx_req_r,
             rx_reset_ovrd_en,
             rx_reset_r
             }),
    .cr_rd_data(cr_rx_ovrd_in_1_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_rx_ovrd_in_1),
    .cr_self_clr (1'b0)
);

// %%CREG RX_OVRD_IN_2 - Override values for incoming RX controls from PCS, register #2
//   OFFSET: 0x7
//   ATTR:   RW, CUST
//   FIELDS:
//     [15] VCO_LOWFREQ_VAL_OVRD_EN   - Enable override for rx_cdr_vco_lowfreq
//          RESET: 0x0
//     [14] VCO_LOWFREQ_VAL_OVRD     - Override value for rx_cdr_vco_lowfreq
//          RESET: 0x0
//     [13] VCO_LD_VAL_OVRD_EN       - Enable override for rx_vco_ld_val
//          RESET: 0x0
//   [12:0] VCO_LD_VAL_OVRD          - Override value for rx_vco_ld_val
//          RESET: 0x0
//
wire        rx_cdr_vco_lowfreq_ovrd_en;
wire        rx_cdr_vco_lowfreq_ovrd_val;
wire        rx_vco_ld_val_ovrd_en;
wire [12:0] rx_vco_ld_val_ovrd_val;
wire        cr_sel_rx_ovrd_in_2 = cr_sel[7];
wire [15:0] cr_rx_ovrd_in_2_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(16), .RST_VAL(16'h0000), .MSK_VAL(16'd0))
  rx_ovrd_in_2_reg (
    .cr_val({
             rx_cdr_vco_lowfreq_ovrd_en,
             rx_cdr_vco_lowfreq_ovrd_val,
             rx_vco_ld_val_ovrd_en,
             rx_vco_ld_val_ovrd_val
             }),
    .cr_rd_data(cr_rx_ovrd_in_2_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_rx_ovrd_in_2),
    .cr_self_clr (1'b0)
);

// %%CREG RX_OVRD_IN_3 - Override values for incoming RX controls from PCS, register #3
//   OFFSET: 0x8
//   ATTR:   RW, CUST
//   FIELDS:
//     [15] CONT_OVRD_EN       - Enable override values for rx_adapt_cont and rx_offcan_cont
//          RESET: 0x0
//     [14] OFFCAN_CONT        - Override value for rx_offcan_cont
//          RESET: 0x0
//     [13] ADAPT_CONT         - Override value for rx_adapt_cont
//          RESET: 0x0
//     [12] ADAPT_REQ_OVRD_EN  - Enable override values for rx_adapt_req
//          RESET: 0x0
//     [11] ADAPT_REQ          - Override value for rx_adapt_req
//          RESET: 0x0
//     [10] REF_LD_VAL_OVRD_EN - Enable override for rx_ref_ld_val
//          RESET: 0x0
//    [9:4] REF_LD_VAL_OVRD    - Override value for rx_ref_ld_val
//          RESET: 0x0
//      [3] RX_LOS_THRSHLD_OVRD_EN   - Enable override for rx_los_threshold
//          RESET: 0x0
//    [2:0] RX_LOS_THRSHLD_OVRD_VAL  - Override value for rx_los_threshold
//          RESET: 0x0
//
wire        rx_cont_ovrd_en;
wire        rx_offcan_cont_r;
wire        rx_adapt_cont_r;
wire        rx_adapt_req_r;
wire        rx_adapt_req_ovrd_en;
wire        rx_ref_ld_val_ovrd_en;
wire [5:0]  rx_ref_ld_val_ovrd_val;
wire        rx_los_threshold_ovrd_en;
wire  [2:0] rx_los_threshold_ovrd_val;
wire        cr_sel_rx_ovrd_in_3 = cr_sel[8];
wire [15:0] cr_rx_ovrd_in_3_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(16), .RST_VAL(16'h0000), .MSK_VAL(16'd0))
  rx_ovrd_in_3_reg (
    .cr_val({
             rx_cont_ovrd_en,
             rx_offcan_cont_r,
             rx_adapt_cont_r,
             rx_adapt_req_ovrd_en,
             rx_adapt_req_r,
             rx_ref_ld_val_ovrd_en,
             rx_ref_ld_val_ovrd_val,
             rx_los_threshold_ovrd_en,
             rx_los_threshold_ovrd_val
             }),
    .cr_rd_data(cr_rx_ovrd_in_3_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_rx_ovrd_in_3),
    .cr_self_clr (1'b0)
);

// Mantis 6810 - 
// In scan mode, rx_reset_i will have scan muxed onto it, and therefore
// cannot be sent to a synchronizer directly.  Instead send an arbitrary
// register on the same clock domain in scan mode to maintain coverage.
dwc_e12mp_phy_x4_ns_gen_mux rx_reset_mux (
  .out (rx_reset_int),
  .sel (scan_mode_i),
  .d0  (rx_reset_ate),
  .d1  (rx_reset_r)
);

// %%CREG RX_PCS_IN - Current values for incoming RX controls from PCS
//   OFFSET: 0x9
//   ATTR: READ, VOL, CUST
//   FIELDS:
//     [14] RESET             - Value from PCS for rx_reset
//     [13] OFFCAN_CONT       - Value from PCS for rx_offcan_cont
//     [12] ADAPT_CONT        - Value from PCS for rx_adapt_cont
//     [11] ADAPT_REQ         - Value from PCS for rx_adapt_req
//     [10] ADAPT_DFE_EN      - Value from PCS for rx_adapt_dfe_en
//      [9] ADAPT_AFE_EN      - Value from PCS for rx_adapt_afe_en
//      [8] CDR_VCO_LOWFREQ   - Value from PCS for rx_cdr_vco_lowfreq
//      [7] LPD               - Value from PCS for rx_lpd
//    [6:5] PSTATE            - Value from PCS for rx_pstate
//    [4:3] WIDTH             - Value from PCS for rx_width
//    [2:1] RATE              - Value from PCS for rx_rate
//      [0] REQ               - Value from PCS for rx_req
//
wire        cr_sel_rx_pcs_in = cr_sel[9];
wire [15:0] cr_rx_pcs_in_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(15))
  rx_pcs_in_reg (
    .cr_val({
             rx_reset_int,
             rx_offcan_cont,
             rx_adapt_cont,
             rx_adapt_req,
             rx_adapt_dfe_en,
             rx_adapt_afe_en,
             rx_cdr_vco_lowfreq,
             rx_lpd,
             rx_pstate,
             rx_width,
             rx_rate,
             rx_req
             }),
    .cr_rd_data(cr_rx_pcs_in_rd_data),
    .cr_sel(cr_sel_rx_pcs_in)
);

// %%CREG RX_PCS_IN_1 - Current values for incoming RX controls from PCS, register #1
//   OFFSET: 0xA
//   ATTR: READ, VOL, CUST
//   FIELDS:
//    [5:0] REF_LD_VAL        - Value from PCS for rx_ref_ld_val
//
wire        cr_sel_rx_pcs_in_1 = cr_sel[10];
wire [15:0] cr_rx_pcs_in_1_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(6))
  rx_pcs_in_1_reg (
    .cr_val({
             rx_ref_ld_val
             }),
    .cr_rd_data(cr_rx_pcs_in_1_rd_data),
    .cr_sel(cr_sel_rx_pcs_in_1)
);

// %%CREG RX_PCS_IN_2 - Current values for incoming RX controls from PCS, register #2
//   OFFSET: 0xB
//   ATTR: READ, VOL, CUST
//   FIELDS:
//   [12:0] VCO_LD_VAL        - Value from PCS for rx_vco_ld_val
//
wire        cr_sel_rx_pcs_in_2 = cr_sel[11];
wire [15:0] cr_rx_pcs_in_2_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(13))
  rx_pcs_in_2_reg (
    .cr_val({
             rx_vco_ld_val
             }),
    .cr_rd_data(cr_rx_pcs_in_2_rd_data),
    .cr_sel(cr_sel_rx_pcs_in_2)
);

// %%CREG RX_PCS_IN_3 - Current values for incoming RX controls from PCS, register #3
//   OFFSET: 0xC
//   ATTR: READ, VOL, CUST
//   FIELDS:
//  [15:11] EQ_CTLE_BOOST    - Value from ASIC for rx_eq_ctle_boost
//   [10:7] EQ_VGA2_GAIN     - Value from ASIC for rx_eq_vga2_gain
//    [6:3] EQ_VGA1_GAIN     - Value from ASIC for rx_eq_vga1_gain
//    [2:0] EQ_ATT_LVL       - Value from ASIC for rx_eq_att_lvl
//
wire        cr_sel_rx_pcs_in_3 = cr_sel[12];
wire [15:0] cr_rx_pcs_in_3_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(16))
  rx_pcs_in_3_reg (
    .cr_val({
             rx_eq_ctle_boost,
             rx_eq_vga2_gain,
             rx_eq_vga1_gain,
             rx_eq_att_lvl
             }),
    .cr_rd_data(cr_rx_pcs_in_3_rd_data),
    .cr_sel(cr_sel_rx_pcs_in_3)
);

// %%CREG RX_PCS_IN_4 - Current values for incoming RX controls from PCS, register #4
//   OFFSET: 0xD
//   ATTR: READ, VOL, CUST
//   FIELDS:
//   [10:3] EQ_DFE_TAP1      - Value from ASIC for rx_eq_dfe_tap1
//    [2:0] EQ_CTLE_POLE     - Value from ASIC for rx_eq_ctle_pole
//
wire        cr_sel_rx_pcs_in_4 = cr_sel[13];
wire [15:0] cr_rx_pcs_in_4_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(11))
  rx_pcs_in_4_reg (
    .cr_val({
             rx_eq_dfe_tap1,
             rx_eq_ctle_pole
             }),
    .cr_rd_data(cr_rx_pcs_in_4_rd_data),
    .cr_sel(cr_sel_rx_pcs_in_4)
);

// %%CREG RX_OVRD_OUT - Override values for outgoing RX controls to PCS
//   OFFSET: 0xE
//   ATTR:   RW, CUST
//   FIELDS:
//      [1] EN_CTL       - Enable override values for all control outputs of this register
//          RESET: 0x1
//      [0] ACK          - Override value for rx_ack
//          RESET: 0x1
//
wire        rx_ovrd_out_en;
wire        rx_ack_r;
wire        cr_sel_rx_ovrd_out = cr_sel[14];
wire [15:0] cr_rx_ovrd_out_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(2), .RST_VAL(2'b1_1), .MSK_VAL(2'd0))
  rx_ovrd_out_reg (
    .cr_val({
             rx_ovrd_out_en,
             rx_ack_r
             }),
    .cr_rd_data(cr_rx_ovrd_out_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_rx_ovrd_out),
    .cr_self_clr (1'b0)
);

// %%CREG RX_PCS_OUT - Current values for outgoing RX status controls from Raw PCS
//   OFFSET: 0xF
//   ATTR: READ, VOL, CUST
//   FIELDS:
//      [0] ACK     - Value from Raw PCS for rx_ack
//
wire        cr_sel_rx_pcs_out = cr_sel[15];
wire [15:0] cr_rx_pcs_out_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(1))
  rx_pcs_out_reg (
    .cr_val({
             rx_ack_i
             }),
    .cr_rd_data(cr_rx_pcs_out_rd_data),
    .cr_sel(cr_sel_rx_pcs_out)
);

// %%CREG RX_ADAPT_ACK - RX Adaptation Acknowledge
//   OFFSET: 0x10
//   ATTR:   RW, CUST
//   FIELDS:
//      [0] RX_ADAPT_ACK       - RX Adaptation Acknowledge
//          RESET: 0x0
wire        rx_adapt_ack_r;
wire        cr_sel_rx_adapt_ack = cr_sel[16];
wire [15:0] cr_rx_adapt_ack_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(1), .RST_VAL(1'b0), .MSK_VAL(1'd0))
  rx_adapt_ack_reg (
    .cr_val({
             rx_adapt_ack_r
             }),
    .cr_rd_data(cr_rx_adapt_ack_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_rx_adapt_ack),
    .cr_self_clr(1'b0)
);

// %%CREG RX_ADAPT_FOM - RX Adaptation Figure of Merit
//   OFFSET: 0x11
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] RX_ADAPT_FOM     - RX Adaptation Figure of Merit
//          RESET: 0x0
wire [7:0]  rx_adapt_fom_r;
wire        cr_sel_rx_adapt_fom = cr_sel[17];
wire [15:0] cr_rx_adapt_fom_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h00), .MSK_VAL(8'd0))
  rx_adapt_fom_reg (
    .cr_val({
             rx_adapt_fom_r
             }),
    .cr_rd_data(cr_rx_adapt_fom_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_rx_adapt_fom),
    .cr_self_clr(1'b0)
);

// %%CREG RX_TXPRE_DIR - RX calculated direction for TX-pre
//   OFFSET: 0x12
//   ATTR:   RW, CUST
//   FIELDS:
//    [1:0] RX_TXPRE_DIR     - RX calculated direction for TX-pre
//          NOTES:             00 - No change
//                             01 - Increment
//                             10 - Decrement
//                             11 - Reserved
//          RESET: 0x0
wire [1:0]  rx_txpre_dir_r;
wire        cr_sel_rx_txpre_dir = cr_sel[18];
wire [15:0] cr_rx_txpre_dir_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(2), .RST_VAL(2'b00), .MSK_VAL(2'd0))
  rx_txpre_dir_reg (
    .cr_val({
             rx_txpre_dir_r
             }),
    .cr_rd_data(cr_rx_txpre_dir_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_rx_txpre_dir),
    .cr_self_clr(1'b0)
);

// %%CREG RX_TXMAIN_DIR - RX calculated direction for TX-Main
//   OFFSET: 0x13
//   ATTR:   RW, CUST
//   FIELDS:
//    [1:0] RX_TXMAIN_DIR     - RX calculated direction for TX-Main
//          NOTES:              00 - No change
//                              01 - Increment
//                              10 - Decrement
//                              11 - Reserved
//          RESET: 0x0
wire [1:0]  rx_txmain_dir_r;
wire        cr_sel_rx_txmain_dir = cr_sel[19];
wire [15:0] cr_rx_txmain_dir_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(2), .RST_VAL(2'b00), .MSK_VAL(2'd0))
  rx_txmain_dir_reg (
    .cr_val({
             rx_txmain_dir_r
             }),
    .cr_rd_data(cr_rx_txmain_dir_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_rx_txmain_dir),
    .cr_self_clr(1'b0)
);

// %%CREG RX_TXPOST_DIR - RX calculated direction for TX-Post
//   OFFSET: 0x14
//   ATTR:   RW, CUST
//   FIELDS:
//    [1:0] RX_TXPOST_DIR     - RX calculated direction for TX-Post
//          NOTES:              00 - No change
//                              01 - Increment
//                              10 - Decrement
//                              11 - Reserved
//          RESET: 0x0
wire [1:0]  rx_txpost_dir_r;
wire        cr_sel_rx_txpost_dir = cr_sel[20];
wire [15:0] cr_rx_txpost_dir_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(2), .RST_VAL(2'b00), .MSK_VAL(2'd0))
  rx_txpost_dir_reg (
    .cr_val({
             rx_txpost_dir_r
             }),
    .cr_rd_data(cr_rx_txpost_dir_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_rx_txpost_dir),
    .cr_self_clr(1'b0)
);

// %%CREG LANE_NUMBER - Current lane number
//   OFFSET: 0x15
//   ATTR: READ, VOL, CUST
//   FIELDS:
//    [3:0] LANE_NUMBER     - Current lane number
//
wire        cr_sel_chan_addr_in = cr_sel[21];
wire [15:0] cr_chan_addr_in_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(4))
  chan_addr_in_reg (
    .cr_val({
             cr_chan_addr
             }),
    .cr_rd_data(cr_chan_addr_in_rd_data),
    .cr_sel(cr_sel_chan_addr_in)
);

// Mantis 6933 - Add an additional layer of registers for ATE
// Mantis 7140 - Fix ATE_OVRD_IN register offset
// %%CREG ATE_OVRD_IN - ATE Override input to control top-level inputs
//   OFFSET: 0x16
//   ATTR:   RW, CUST
//   FIELDS:
//      [3] TX_RESET_ATE_OVRD_EN  - Enable override value for tx_reset input
//          RESET: 0x0
//      [2] TX_RESET_ATE_OVRD_VAL - Override value for top-level tx_reset input
//          RESET: 0x0
//      [1] RX_RESET_ATE_OVRD_EN  - Enable override value for rx_reset input
//          RESET: 0x0
//      [0] RX_RESET_ATE_OVRD_VAL - Override value for top-level rx_reset input
//          RESET: 0x0
//
wire        tx_reset_ate_ovrd_en;
wire        tx_reset_ate_ovrd_val;
wire        rx_reset_ate_ovrd_en;
wire        rx_reset_ate_ovrd_val;
wire        cr_sel_ate_ovrd_in = cr_sel[22];
wire [15:0] cr_ate_ovrd_in_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(4), .RST_VAL(4'b00_00), .MSK_VAL(4'd0))
  ate_ovrd_in_reg (
    .cr_val({
             tx_reset_ate_ovrd_en,
             tx_reset_ate_ovrd_val,
             rx_reset_ate_ovrd_en,
             rx_reset_ate_ovrd_val
             }),
    .cr_rd_data(cr_ate_ovrd_in_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_ate_ovrd_in),
    .cr_self_clr (1'b0)
);

// %%CREG RX_OVRD_OUT_1 - Override values for outgoing RX controls to PCS, register #1
//   OFFSET: 0x17
//   ATTR:   RW, CUST
//   FIELDS:
//      [0] RX_CLK_EN    - Enable the outging rx_clk
//          RESET: 0x1
//
wire        rx_clk_en_r;
wire        cr_sel_rx_ovrd_out_1 = cr_sel[23];
wire [15:0] cr_rx_ovrd_out_1_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(1), .RST_VAL(1'b1), .MSK_VAL(1'd0))
  rx_ovrd_out_1_reg (
    .cr_val({
             rx_clk_en_r
             }),
    .cr_rd_data(cr_rx_ovrd_out_1_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_rx_ovrd_out_1),
    .cr_self_clr (1'b0)
);

`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
//----------------------------------------------------------------------------
// %%CREG RX_OVRD_IN_4 -  Maximum RX CDR PPM value override register
//   OFFSET: 0x18
//   ATTR: READ,WRITE
//   FIELDS:
//      [5] RX_CDR_PPM_MAX_OVRD_EN  - Enable overidde for the RX CDR PPM Max
//          NOTES:                     Input signals overridden by it:
//                                       rx_cdr_ppm_max
//          RESET: 0x0
//    [4:0] RX_CDR_PPM_MAX_OVRD      - Overidden value for RX CDR PPM Max. 
//          NOTES:                     Its override enable is:
//                                       RX_OVRD_IN_4.RX_CDR_PPM_MAX_OVRD_EN
//          RESET: 0x0
//
wire        rx_cdr_ppm_max_ovrd_en;
wire [4:0]  rx_cdr_ppm_max_ovrd_val;
wire [15:0] cr_rx_ovrd_in_4_rd_data;
wire        cr_sel_rx_ovrd_in_4 = cr_sel[24];
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(6), .RST_VAL(6'b00000_0), .MSK_VAL(6'd0))
  rx_ovrd_in_4_reg (
    .cr_val({
             rx_cdr_ppm_max_ovrd_en,
             rx_cdr_ppm_max_ovrd_val
             }),
    .cr_rd_data(cr_rx_ovrd_in_4_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_rx_ovrd_in_4),
    .cr_self_clr (1'b0)
);
`endif

// Generate final control register read data for this module
//
assign cr_rd_data = (
                     cr_tx_ovrd_in_rd_data    |
                     cr_tx_pcs_in_rd_data     |
                     cr_tx_ovrd_out_rd_data   |
                     cr_tx_pcs_out_rd_data    |
                     cr_rx_ovrd_in_rd_data    |
                     cr_rx_ovrd_in_1_rd_data  |
                     cr_rx_ovrd_in_2_rd_data  |
                     cr_rx_ovrd_in_3_rd_data  |
                     cr_rx_pcs_in_rd_data     |
                     cr_rx_pcs_in_1_rd_data   |
                     cr_rx_pcs_in_2_rd_data   |
                     cr_rx_pcs_in_3_rd_data   |
                     cr_rx_pcs_in_4_rd_data   |
                     cr_rx_ovrd_out_rd_data   |
                     cr_rx_pcs_out_rd_data    |
                     cr_rx_adapt_ack_rd_data  |
                     cr_rx_adapt_fom_rd_data  |
                     cr_rx_txpre_dir_rd_data  |
                     cr_rx_txmain_dir_rd_data |
                     cr_rx_txpost_dir_rd_data |
                     cr_chan_addr_in_rd_data  |
                     cr_tx_ovrd_in_1_rd_data  |
                     cr_ate_ovrd_in_rd_data   |
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
                     cr_rx_ovrd_out_1_rd_data |
                     cr_rx_ovrd_in_4_rd_data
`else
                     cr_rx_ovrd_out_1_rd_data
`endif
                    );


////////////////////
// Inputs
////////////////////

assign mplla_init_cal_disable_i = mplla_init_cal_disable;
assign mpllb_init_cal_disable_i = mpllb_init_cal_disable;
assign lane_tx2rx_ser_lb_en_i   = lane_tx2rx_ser_lb_en;
assign lane_rx2tx_par_lb_en_i   = lane_rx2tx_par_lb_en;
assign tx_clk_i     = tx_clk;
assign tx_clk_rdy_i = tx_clk_rdy;
assign tx_data_i    = tx_data;
assign tx_data_en_i = tx_data_en;
assign tx_invert_i  = tx_invert;

// TX inputs
dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(2)) tx_pstate_in (
  .asic           (tx_pstate),
  .phy            (tx_pstate_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (2'b00),
  .cr_ovrd        (tx_ovrd_in_en),
  .cr_ovrd_val    (tx_pstate_r)
);

dwc_e12mp_phy_x4_ns_asic_in tx_lpd_in (
  .asic           (tx_lpd),
  .phy            (tx_lpd_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (tx_ovrd_in_en),
  .cr_ovrd_val    (tx_lpd_r)
);

dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(2)) tx_width_in (
  .asic           (tx_width),
  .phy            (tx_width_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (2'b11),
  .cr_ovrd        (tx_ovrd_in_en),
  .cr_ovrd_val    (tx_width_r)
);

dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(3)) tx_rate_in (
  .asic           (tx_rate),
  .phy            (tx_rate_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (3'b000),
  .cr_ovrd        (tx_ovrd_in_en),
  .cr_ovrd_val    (tx_rate_r)
);

dwc_e12mp_phy_x4_ns_asic_in tx_mpllb_sel_in (
  .asic           (tx_mpllb_sel),
  .phy            (tx_mpllb_sel_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (tx_ovrd_in_en),
  .cr_ovrd_val    (tx_mpllb_sel_r)
);

dwc_e12mp_phy_x4_ns_asic_in tx_mpll_en_in (
  .asic           (tx_mpll_en),
  .phy            (tx_mpll_en_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (tx_ovrd_in_en),
  .cr_ovrd_val    (tx_mpll_en_r)
);

dwc_e12mp_phy_x4_ns_asic_in tx_master_mplla_state_in (
  .asic           (tx_master_mplla_state),
  .phy            (tx_master_mplla_state_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (tx_ovrd_in_en),
  .cr_ovrd_val    (tx_master_mplla_state_r)
);

dwc_e12mp_phy_x4_ns_asic_in tx_master_mpllb_state_in (
  .asic           (tx_master_mpllb_state),
  .phy            (tx_master_mpllb_state_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (tx_ovrd_in_en),
  .cr_ovrd_val    (tx_master_mpllb_state_r)
);

dwc_e12mp_phy_x4_ns_asic_in tx_reset_in (
  .asic           (tx_reset_ate),
  .phy            (tx_reset_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (tx_reset_ovrd_en),
  .cr_ovrd_val    (tx_reset_r)
);

dwc_e12mp_phy_x4_ns_asic_in tx_req_in (
  .asic           (tx_req),
  .phy            (tx_req_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (tx_req_ovrd_en),
  .cr_ovrd_val    (tx_req_r)
);

dwc_e12mp_phy_x4_ns_asic_in tx_detrx_req_in (
  .asic           (tx_detrx_req),
  .phy            (tx_detrx_req_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (tx_detrx_req_ovrd_en),
  .cr_ovrd_val    (tx_detrx_req_r)
);

dwc_e12mp_phy_x4_ns_asic_in tx_vboost_en_in (
  .asic           (tx_vboost_en),
  .phy            (tx_vboost_en_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (tx_vboost_en_ovrd_en),
  .cr_ovrd_val    (tx_vboost_en_ovrd_val)
);

dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(4)) tx_iboost_lvl_in (
  .asic           (tx_iboost_lvl),
  .phy            (tx_iboost_lvl_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (4'b0000),
  .cr_ovrd        (tx_iboost_lvl_ovrd_en),
  .cr_ovrd_val    (tx_iboost_lvl_ovrd_val)
);

// Mantis 6933 - Add ATE overrides before other overrides
dwc_e12mp_phy_x4_ns_asic_in tx_reset_ate_in (
  .asic           (tx_reset),
  .phy            (tx_reset_ate),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (tx_reset_ate_ovrd_en),
  .cr_ovrd_val    (tx_reset_ate_ovrd_val)
);

dwc_e12mp_phy_x4_ns_asic_in rx_reset_ate_in (
  .asic           (rx_reset),
  .phy            (rx_reset_ate),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (rx_reset_ate_ovrd_en),
  .cr_ovrd_val    (rx_reset_ate_ovrd_val)
);

// RX inputs
dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(2)) rx_rate_in (
  .asic           (rx_rate),
  .phy            (rx_rate_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (2'b00),
  .cr_ovrd        (rx_ovrd_in_en),
  .cr_ovrd_val    (rx_rate_r)
);

dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(2)) rx_width_in (
  .asic           (rx_width),
  .phy            (rx_width_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (2'b11),
  .cr_ovrd        (rx_ovrd_in_en),
  .cr_ovrd_val    (rx_width_r)
);

dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(2)) rx_pstate_in (
  .asic           (rx_pstate),
  .phy            (rx_pstate_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (2'b00),
  .cr_ovrd        (rx_ovrd_in_en),
  .cr_ovrd_val    (rx_pstate_r)
);

dwc_e12mp_phy_x4_ns_asic_in rx_lpd_in (
  .asic           (rx_lpd),
  .phy            (rx_lpd_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (rx_ovrd_in_en),
  .cr_ovrd_val    (rx_lpd_r)
);

dwc_e12mp_phy_x4_ns_asic_in rx_adapt_afe_en_in (
  .asic           (rx_adapt_afe_en),
  .phy            (rx_adapt_afe_en_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (rx_ovrd_in_en),
  .cr_ovrd_val    (rx_adapt_afe_en_r)
);

dwc_e12mp_phy_x4_ns_asic_in rx_adapt_dfe_en_in (
  .asic           (rx_adapt_dfe_en),
  .phy            (rx_adapt_dfe_en_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (rx_ovrd_in_en),
  .cr_ovrd_val    (rx_adapt_dfe_en_r)
);

dwc_e12mp_phy_x4_ns_asic_in rx_reset_in (
  .asic           (rx_reset_ate),
  .phy            (rx_reset_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (rx_reset_ovrd_en),
  .cr_ovrd_val    (rx_reset_r)
);

dwc_e12mp_phy_x4_ns_asic_in rx_req_in (
  .asic           (rx_req),
  .phy            (rx_req_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (rx_req_ovrd_en),
  .cr_ovrd_val    (rx_req_r)
);

dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(13)) rx_vco_ld_val_in (
  .asic           (rx_vco_ld_val),
  .phy            (rx_vco_ld_val_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (13'd0),
  .cr_ovrd        (rx_vco_ld_val_ovrd_en),
  .cr_ovrd_val    (rx_vco_ld_val_ovrd_val)
);

dwc_e12mp_phy_x4_ns_asic_in rx_cdr_vco_lowfreq_in (
  .asic           (rx_cdr_vco_lowfreq),
  .phy            (rx_cdr_vco_lowfreq_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (rx_cdr_vco_lowfreq_ovrd_en),
  .cr_ovrd_val    (rx_cdr_vco_lowfreq_ovrd_val)
);

dwc_e12mp_phy_x4_ns_asic_in rx_adapt_req_in (
  .asic           (rx_adapt_req),
  .phy            (rx_adapt_req_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (rx_adapt_req_ovrd_en),
  .cr_ovrd_val    (rx_adapt_req_r)
);

dwc_e12mp_phy_x4_ns_asic_in rx_adapt_cont_in (
  .asic           (rx_adapt_cont),
  .phy            (rx_adapt_cont_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (rx_cont_ovrd_en),
  .cr_ovrd_val    (rx_adapt_cont_r)
);

dwc_e12mp_phy_x4_ns_asic_in rx_offcan_cont_in (
  .asic           (rx_offcan_cont),
  .phy            (rx_offcan_cont_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (rx_cont_ovrd_en),
  .cr_ovrd_val    (rx_offcan_cont_r)
);

dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(6)) rx_ref_ld_val_in (
  .asic           (rx_ref_ld_val),
  .phy            (rx_ref_ld_val_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (6'd0),
  .cr_ovrd        (rx_ref_ld_val_ovrd_en),
  .cr_ovrd_val    (rx_ref_ld_val_ovrd_val)
);

dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(3)) rx_los_threshold_in (
  .asic           (rx_los_threshold),
  .phy            (rx_los_threshold_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (3'd0),
  .cr_ovrd        (rx_los_threshold_ovrd_en),
  .cr_ovrd_val    (rx_los_threshold_ovrd_val)
);

`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(5)) rx_cdr_ppm_max_in (
  .asic           (rx_cdr_ppm_max),
  .phy            (rx_cdr_ppm_max_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (5'd0),
  .cr_ovrd        (rx_cdr_ppm_max_ovrd_en),
  .cr_ovrd_val    (rx_cdr_ppm_max_ovrd_val)
);
`endif

assign rx_eq_att_lvl_i    = rx_eq_att_lvl;
assign rx_eq_vga1_gain_i  = rx_eq_vga1_gain;
assign rx_eq_vga2_gain_i  = rx_eq_vga2_gain;
assign rx_eq_ctle_pole_i  = rx_eq_ctle_pole;
assign rx_eq_ctle_boost_i = rx_eq_ctle_boost;
assign rx_eq_dfe_tap1_i   = rx_eq_dfe_tap1;
assign rx_data_en_i       = rx_data_en;
assign rx_cdr_track_en_i  = rx_cdr_track_en;

assign scan_mode_i     = scan_mode;
assign scan_shift_cg_i = scan_shift_cg;
assign scan_set_rst_i  = scan_set_rst;

////////////////////
// Outputs
////////////////////
dwc_e12mp_phy_x4_ns_asic_out tx_ack_out (
  .asic           (tx_ack),
  .phy            (tx_ack_i),
  .cr_ovrd        (tx_ovrd_out_en),
  .cr_ovrd_val    (tx_ack_r)
);
dwc_e12mp_phy_x4_ns_asic_out tx_detrx_result_out (
  .asic           (tx_detrx_result),
  .phy            (tx_detrx_result_i),
  .cr_ovrd        (tx_ovrd_out_en),
  .cr_ovrd_val    (tx_detrx_result_r)
);
dwc_e12mp_phy_x4_ns_asic_out rx_ack_out (
  .asic           (rx_ack),
  .phy            (rx_ack_i),
  .cr_ovrd        (rx_ovrd_out_en),
  .cr_ovrd_val    (rx_ack_r)
);
assign rx_los        = rx_los_i;
assign rx_valid      = rx_valid_i;
assign rx_adapt_ack  = rx_adapt_ack_r;
assign rx_adapt_fom  = rx_adapt_fom_r;
assign rx_txmain_dir = rx_txmain_dir_r;
assign rx_txpre_dir  = rx_txpre_dir_r;
assign rx_txpost_dir = rx_txpost_dir_r;

// Mantis 7172 - Add a clock gate to the rx_clk output so firmware
// can disable it during POR calibration
// Generate a synchronous reset on the ungated rx_clk_i
// Note that to prevent C-26 DFt violations, we mux in a different
// value during scan mode or else the reset is captured by the
// ATPG flop in the pcs_raw_gen_rst_sync
wire rx_clk_en_rx_clk;
wire rx_reset_i_int;
dwc_e12mp_phy_x4_ns_gen_mux rx_reset_i_mux (
  .out (rx_reset_i_int),
  .sel (scan_mode_i),
  .d0  (rx_reset_i),
  .d1  (rx_clk_en_rx_clk)
);

// Mantis 7223 Remove ATPG coverage flop for cascaded pcs_raw_gen_rst_sync
wire rx_clk_rst;
dwc_e12mp_phy_x4_ns_pcs_raw_gen_rst_sync  #(.ATPG_COV(0)) rx_clk_rst_sync (
  .sync_rst       (rx_clk_rst),
  .clk            (rx_clk_i),
  .async_rst      (rx_reset_i_int), // Use the post-override reset
  .scan_mode_i    (scan_mode_i),
  .scan_set_rst_i (scan_set_rst_i)
);

// Synchronize the register output to rx_clk
dwc_e12mp_phy_x4_ns_gen_sync sync_rx_clk_en_rx_clk (
  .q   (rx_clk_en_rx_clk),
  .clk (rx_clk_i),
  .rst (rx_clk_rst),
  .d   (rx_clk_en_r)
);

// Gate the clock
dwc_e12mp_phy_x4_ns_gen_clk_gate rx_clk_gate(
  .en_clk          (rx_clk),
  .clk             (rx_clk_i),
  .rst             (rx_clk_rst),
  .en              (rx_clk_en_rx_clk),
  .scan_mode_i     (scan_mode_i),
  .scan_shift_cg_i (scan_shift_cg_i),
  .scan_set_rst_i  (scan_set_rst_i)
);

endmodule

